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Design and development of Direct Digital Synthesizer on FPGA

C Lohith, Caren B Jacob, Deepika K V, D Puneeth Pavan

Rashmi Priyadarshani.

School of Electronics and communication, REVA University, India.



This paper presents an analysis of a Direct Digital Synthesizer implemented on FPGA using a Hardware Descriptive Language- Verilog. DDS is a frequency synthesizer which can generate arbitrary waveforms from a single reference clock of fixed frequency. FPGA board is used to design a DDS to satisfy different demands of the user. DDS helps in achieving the requirements of fast frequency and phase switching, signals with high frequency and superior quality and also high range of tuneable frequencies.


Keywords: DDS, FPGA, LUT, Verilog.



1.1 What is DDS?

Direct digital synthesis (DDS) is a method of producing an analog waveform, usually a sine wave, by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binary number programmed into the frequency register (tuning word). DDS devices are not limited to purely sinusoidal outputs, they can also have square and triangular outputs. DDS is a method employed by frequency synthesizers used for creating arbitrary waveforms from a single, fixed-frequency reference clock. DDS is used in applications such as signal generation, local oscillators in communication systems, function generators, mixers, modulators, sound synthesizers and as part of a digital phase-locked loop.

  • Uses of DDS

The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low phase-noise variable-frequencies with good spurious performance for communications or simply generating a frequency stimulus in industrial; convenience, compactness, and low cost are important design considerations. Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy. DDS devices are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and reprogram) the output waveform, make DDS devices an efficient solution.



Through research of a bunch of papers and a other articles makes it evident that DDS has a great potential in radio frequecies and it is used in its various applications.

2.1 Kenneth A. Essenwanger[1]  has stated that “DDSs have been in use since the late 1960s [Gillette, 1969] and have become more and more popular as digital logic has advanced in complexity and performance. Sine output DDSs are not the only type of DDSs [Reinhardt, 1985], but have become the most widely used because of their high spectral purity and all digital implementation.”


2.2 Amir M. Sodagar[2]  in his paper has stated a different approach for frequency synthesis-The simplest implementation of parabolic approximation  idea is to use the value of phase as the initial guess. This method, which is called “sine- phase difference” technique, saves 2 bits of memory word length [2–5]. Another similar work implementing the above idea is a double trigonometric approximation which has led to a memory word length reduction of 3 bits. The closest initial guess to the target sinusoid is obtained by using parabolic approximation.”



DDS consists of four modules of phase accumulator, phase converter, digital analog converter and low pass filter, which control the synchronization of all parts of DDS through clock frequency (clk). In this paper, FPGA technology is used to design the various modules with Verilog HDL language, and combined with Fig. 2, the overall structure of the modified DDS is presented as shown in Fig. 3.


The frequency of the output waveform can be controlled by two variables, those are:

  • The reference clock frequency (the input clock signal that you feed into the DDS).
  • The variable programmed into the delta phase register, called the tuning word or M.

The phase accumulator is the most important part in the system, every clock cycle a number called the tuning word is added to the phase accumulator register. The truncated output of the phase accumulator serves as the address to the sine-lookup table and each address in the lookup table corresponds to a phase point on the sine wave from 0° to 360°. Therefore, the lookup table contains the corresponding digital amplitude information for one complete cycle of the wave, and it maps the phase information into a digital amplitude word.

The tuning word provided to the phase accumulator can be rather large or small:

  • Large phase increment: the phase accumulator will step quickly through the sine look-up table and thus generating a high frequency wave.
  • Small phase increment: the phase accumulator will take more steps and generates a low frequency wave.

Phase truncation occurs at the interface between the phase accumulator and the phase-to-amplitude converter. It means that only a subset of the bits at the output of the phase accumulator appear at the input of the phase-to-amplitude converter. For example if we have a DDS that uses a 32-bit accumulator, only the 16 most significant bits get passed along the phase-to-amplitude converter. This is used to reduce the power consumption and complexity of the phase-to-amplitude converter and has no impact on the frequency resolution of the DDS.

The DAC will be then be implemented externally to the FPGA which will convert the digital signal to analog signal which will then be given to a Low Pass Filter(LPF) to filter the noise


Figure 1: A Flexible DDS System





1.       FPGA Board:- Nexys video Artix-7(XC78200T-1SBG484C)

  1. Digital to analog convertor:- MAX512CPD
  2. Oscilloscope

  1. Xilinx VIVADO 2018.3



The present work shows basic DDS implementation proving the design by synthesis on FPGA. Using this type of model we can generate high frequency signals in range of 100 to 200 MHz with high accuracy and its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital control. Another major advantage of this type of model is we can manipulate the code with new ideas which  help to improve the performance of the model with same hardware components.


[1] Kenneth A. Essenwanger and Victor S. Reinhardt, “Sine output DDS’ a survey of the state of the art”, 1998.

[2] Amir M. Sodagar, G. Roientan Lahiji and Ali Azarpeyvand, “Reduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guess”, 30 July 2002.

[3] Miss. P. Chandramani, Abhaya kumar jena, “FPGA Implementation of Direct Digital Frequency Synthesizer for Communication Applications”, 7 July 2015.

[4] Anjali Pawar, “Direct Digital Synthesizer Based on FPGA”, 7 July 2015.

[5] Eva Murphy and Colm Slattery, “All About Direct Digital Synthesis”, August 2014.


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